AXI4-Lite to DDR4 SDRAM Bridge IP Core - DDR4 RAM Access

This core acts as a bridge between the AXI4-Lite register access interface and the Xilinx DDR4 Memory Controller IP core in the Pentek Jade Model 71861. This core is connected to the Xilinx DDR4 Memory Controller IP core through the Pentek AXI4-Stream to DDR4 Memory Controller Interface IP Core in the DDR4 SDRAM Interface Block.

Register Space Memory Map DDR4 RAM Access Base Address = BAR0 + 0x0000_6000
Register Name	Address Offset (Base Address+)	Access	Description
DDR4 Address Register 1	0x00	R/W	Controls the DDR4 SDRAM request address.
DDR4 Address Register 2	0x04	R/W	Controls the DDR4 address expansion bits, memory area, and byte enables.
DDR4 Data Access Register	0x08	R/W	Controls the DDR4 SDRAM data for read/ write operations.

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Lite to DDR4 SDRAM Bridge IP core, the IP user manual is in the file px_axil2ddr_rq.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Lite to DDR4 SDRAM Bridge IP core, the corresponding BSP header file is px_axil2ddr_rq.h.