DDR4 Address Register 2:
This is the DDR4 Address Register 2 in the AXI4-Lite to DDR4 SDRAM Bridge IP core of the PCI Express Interface Block. This register controls the most significant 2 bits of the DDR4 SDRAM address, the memory area, and the byte mask bits.
DDR4 Address Register 2 (Base Address + 0x04) Bits Field Name Default Value Access Type Description 31:8 Reserved N/A N/A Reserved 7:4 byte_mask 0000 R/W Byte Mask Bits: These bits are used to mask the bytes of data to be written to or read from the DDR4 SDRAM. Each bit corresponds to a byte in the 32-bit data of the AXI4-Lite bus. byte_mask[0] corresponds to least significant byte and byte_mask[3] corresponds to the most significant byte. 0 = Byte mask disabled 1 = Byte mask enabled 3 mem_area 0 R/W Memory Area: Data bus of the DDR4 memory is 640 bits wide. Since the maximum output data bus width of this core is 512 bits, mem_area is used to identify the data corresponding to the ranges 0-512 bits and 513-639 bits. Based on this bit the byte mask is defined within the user sideband data of the core. 0 = Data in bits 0 to 512 1 = Data in bits 513 to 639 2:0 ddr4_addr 000 R/W DDR4 Address[34:32]: These bits hold the value of the DDR4 request address bits [34:32].
DDR4 RAM Access Address = BAR0 + 0x0000_6004