PCIe Interfaces

The block diagram below shows the PCIe Interfaces data flow. This block of IP Core modules controls all data I/O for the board’s PCI Express interface and provides access to the board’s I2C devices, Flash memory, and SDRAM memory. You can access register information by clicking on blocks in the diagram.

The memory map for these FPGA IP Core modules is provided in PCI Express Interfaces. For information about the corresponding support software, refer to Board Support Software: Navigator Design Suite.

The following topics describe the IP Cores shown in the block diagram.

• AXI4−Stream Traffic Meter
• FPGA Gen3 PCIe Core
• PCIe To AXI4−Lite Bridge
• Interrupt Controller
• Board Information Registers
• I2C Port 0
• I2C Port 1
• Configuration Flash Access
• DDR4 SDRAM Access
• System Monitor
• ICAP Port