FPGA Gen3 PCIe Core

The FPGA Gen3 PCIe Core provides the AXI4−Stream interface to the FPGA GTH transceivers for PCI Express using the Xilinx Vivado Design Suite LogiCORE IP Core: ultrascale_pcie_gen3.

Refer to the Xilinx UltraScale Architecture Gen3 Integrated Block for PCI Express LogiCORE IP Core Manual for a description of this IP module.