The ICAP Port Core allows the user to read and write the FPGA configuration memory through the Internal Configuration Access Port (ICAP) using the Xilinx Vivado Design Suite LogiCORE IP Core: axi_hwicap.
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Only advanced users who have FPGA reconfiguration experience should use the ICAP port. |
Refer to the Xilinx AXI HWICAP LogiCORE IP Core Manual for a description of this IP module.