AXI4-Lite to NOR Flash Interface IP Core - Configuration Flash Access

This core provides a read/write interface to the Micron PC28F00AG18 parallel NOR Flash memory on the Pentek Jade Model 71861. The 128MB Micron parallel Flash memory is used for processing FPGA boot code.

Register Space Memory Map Configuration Flash Access Base Address = BAR0 + 0x0000_5000
Register Name	Address Offset (Base Address+)	Access	Description
Flash Address Register	0x00	R/W	Controls the Flash address.
Flash Data Register	0x04	R/W	Control the Flash data.

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Lite to NOR Flash Interface IP core, the IP user manual is in the file px_axil2flash.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Lite to NOR Flash Interface IP core, the corresponding BSP header file is px_axil2flash.h.