AXI4-Stream Gate Substitution IP Core - DDC Threshold Gating for Channels 0, 1, 2, and 3

This is the AXI4-Stream Gate Substitution IP Core of the DSP Block for Channels 0 through 3 which provides optional gate substitution of the gate bits within the input AXI4-Stream from the AXI4-Stream IQ Data Format IP core.

Register Space Memory Map Channel 0 DDC Threshold Gating Base Address = BAR0 + 0x0201_2000 Channel 1 DDC Threshold Gating Base Address = BAR0 + 0x0211_2000 Channel 2 DDC Threshold Gating Base Address = BAR0 + 0x0221_2000 Channel 3 DDC Threshold Gating Base Address = BAR0 + 0x0231_2000
Register Name	Address Offset (Base Address+)	Access	Description
Selection Control Register	0x00	R/W	Controls the selection bits of the gate substitution multiplexer.

Register Space Memory Map
Channel 0 DDC Threshold Gating Base Address = BAR0 + 0x0201_2000
Channel 1 DDC Threshold Gating Base Address = BAR0 + 0x0211_2000
Channel 2 DDC Threshold Gating Base Address = BAR0 + 0x0221_2000
Channel 3 DDC Threshold Gating Base Address = BAR0 + 0x0231_2000

Address Offset

(Base Address+)

Access

Description

Selection Control Register

0x00

R/W

Controls the selection bits of the gate substitution multiplexer.

Selection Control Register:

This is the Selection Control Register in the AXI4-Stream Gate Substitution Core for the channels of the DSP Block. This register is used to control the select bits of the gate substitution multiplexer which determines the gate substitution operation on the input AXI4-Stream data of the core.

Selection Control Register (Base Address + 0x00) Channel 0 DDC Threshold Gating Address = BAR0 + 0x0201_2000 Channel 1 DDC Threshold Gating Address = BAR0 + 0x0211_2000 Channel 2 DDC Threshold Gating Address = BAR0 + 0x0221_2000 Channel 3 DDC Threshold Gating Address = BAR0 + 0x0231_2000
Bits	Field Name	Default Value	Access Type	Description
31:2	Reserved	N/A	N/A	Reserved
1:0	select_bits	00	R/W	Select Bits: These bits are the select bits of the gate substitution multiplexer. 00 - Normal gate passed through without substitution 01 - User input gate substituted in the gate bits of input AXI4-Stream 10, 11 - Output of AND operation of the user gate input and normal gate in the input AXI4-Stream is substituted in the gate bits

Selection Control Register (Base Address + 0x00)
Channel 0 DDC Threshold Gating Address = BAR0 + 0x0201_2000
Channel 1 DDC Threshold Gating Address = BAR0 + 0x0211_2000
Channel 2 DDC Threshold Gating Address = BAR0 + 0x0221_2000
Channel 3 DDC Threshold Gating Address = BAR0 + 0x0231_2000

Bits

Field Name

Default

Value

Access

Type

Description

31:2

Reserved

N/A

Reserved

1:0

select_bits

R/W

Select Bits: These bits are the select bits of the gate substitution multiplexer.

00 - Normal gate passed through without substitution

01 - User input gate substituted in the gate bits of input AXI4-Stream

10, 11 - Output of AND operation of the user gate input and normal gate in the input AXI4-Stream is substituted in the gate bits

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Stream Gate Substitution IP core, the IP user manual is in the file px_axispdti_gatesub.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Stream Gate Substitution IP core, the corresponding BSP header file is px_axispdti_gatesub.h.