Data_Acq

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Data Acquisition

Base Address	Module	Description	Link to Register Information	Reference
0x0080_0000	Ch0 Data Acquisition	Outputs Ch0 Data to DMA based on Gate Events	AXI4-Stream Data Flow Control and Packetizer Type-1 IP Core - Data Acquisition Channels 0, 1, 2, and 3	Data Flow Control
0x0080_1000	Ch1 Data Acquisition	Outputs Ch1 Data to DMA based on Gate Events
0x0080_2000	Ch2 Data Acquisition	Outputs Ch2 Data to DMA based on Gate Events
0x0080_3000	Ch3 Data Acquisition	Outputs Ch3 Data to DMA based on Gate Events
	−	Reserved	Reserved	−
0x0080_8000	Ch0 Pre−Trigger Control	Delays Ch0 Data relative to Gate	AXI4-Stream Advance IP Core - Pre-Trigger Control for Channels 0, 1, 2, and 3	Pre−Trigger Control
0x0080_9000	Ch1 Pre−Trigger Control	Delays Ch1 Data relative to Gate
0x0080_A000	Ch2 Pre−Trigger Control	Delays Ch2 Data relative to Gate
0x0080_B000	Ch3 Pre−Trigger Control	Delays Ch3 Data relative to Gate
	−	Reserved	Reserved	−
0x0090_0000	Ch0 DMA	Channel 0 DMA Control Registers	AXI4-Stream to PCI Express (PCIe) Direct Memory Access (DMA) IP Core - DMA for Channels 0, 1, 2, and 3	DMA
0x0092_0000	Ch0 DMA	Channel 0 DMA Linked List Descriptor RAM
0x0094_0000	Ch1 DMA	Channel 1 DMA Control Registers
0x0096_0000	Ch1 DMA	Channel 1 DMA Linked List Descriptor RAM
0x0098_0000	Ch2 DMA	Channel 2 DMA Control Registers
0x009A_0000	Ch2 DMA	Channel 2 DMA Linked List Descriptor RAM
0x009C_0000	Ch3 DMA	Channel 3 DMA Control Registers
0x009E_0000	Ch3 DMA	Channel 3 DMA Linked List Descriptor RAM
0x00D0_0000	Data Acq Interrupts	Interrupt Registers for Data Acquisition	Aggregate Multiple Interrupt Pulses IP Core - Data Acquisition Interrupts	Data Acquisition Interrupts