AXI4-Stream Advance IP Core - Pre-Trigger Control for Channels 0, 1, 2, and 3
This core advances data, timestamp, and data information of the incoming combined data/ timestamp/ information AXI4-Stream from the channels of the Data Acquisition Block, to align with gate/ sync/ PPS events. This core is used as pre-trigger control for ADC channels 0 through 3.
The pre-trigger delay delays the data with respect to the trigger or gate by a programmable number of data samples. When data is DDC data it is in terms of DDC samples. The granularity of the delay depends on the samples/cycle of the product and the data mode.
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When trying to pre-trigger, you should set the post trigger delay to 0 or it will negate it. |
Below are the pre-trigger settings of the 71861:
Raw Data Mode:
Delay Setting = desired number of pre-trigger samples/1
Max Delay = 1*1023
DDC Mode:
Delay Setting = desired number of pre-trigger samples/1
Max Delay = 1*1023
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Register Space Memory Map |
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|---|---|---|---|
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Register Name |
Address Offset (Base Address+) |
Access |
Description |
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Control Register |
0x00 |
R/W |
Controls delay to be introduced to the input data. |
Control Register:
This register controls the delay to be introduced to AXI4-Stream input of this IP core from the channels of the Data Acquisition Block.
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Control Register (Base Address + 0x00) |
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Bits |
Field Name |
Default Value |
Access Type |
Description |
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31:16 |
Reserved |
N/A |
N/A |
Reserved |
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15:0 |
delay_ctl |
0x0000 |
R/W |
Delay Control Value: These bits define the delay to be introduced to the input data stream. |
For more information:
The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Stream Advance IP core, the IP user manual is in the file px_axis_pdti_adv.pdf.
The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Stream Advance IP Core, the corresponding BSP header file is px_axis_pdti_adv.c.