DMA

The PCIe DMA Core for each channel moves the packetized AXI4−Stream (see Data Flow Control) to the PCIe interface (see AXI4−Stream Traffic Meter) using a linked−list DMA methodology. This core also transmits meta data which includes information about the data being moved such as timestamp, transfer length, and start and end of data acquisition markers.

Click on AXI4-Stream to PCI Express (PCIe) Direct Memory Access (DMA) IP Core - DMA for Channels 0, 1, 2, and 3 to access DMA Core register information.

There are two separate memory map addresses for this IP Core (see Data Acquisition): one for the core control registers and one for the Linked List Descriptor RAM.

Refer to the Pentek Navigator AXI4−Stream to PCI Express (PCIe) Direct Memory Access (DMA) IP Core Manual for a description of this IP module.