Pre−Trigger Control

The Pre−Trigger Control Core for each channel delays the combined data/timestamp AXI4−Stream data relative to the Gate/Sync/PPS events to allow the use of data captured prior to the trigger (pre−trigger data).

Click on AXI4-Stream Data Flow Control and Packetizer Type-1 IP Core - Data Acquisition Channels 0, 1, 2, and 3 to access register information.

Refer to the Pentek Navigator AXI4−Stream Advance IP Core Manual for a description of this IP module.

The Pre−Trigger delay delays the data with respect to the trigger or gate by a programmable number of data samples. When data is DDC data it is in terms of DDC samples. The granularity of the delay depends on the samples/cycle of the product and the data mode.

Note also that when trying to pre−trigger, you should set post trigger delay to zero or it will negate it.

Raw Data Mode:

Delay Setting = desired number of pre−trig samples/1

Max Delay = 1*1023

DDC Mode:

Delay Setting = desired number of pre−trig DDC samples/1

Max Delay = 1*1023