Data Acquisition

The diagram below shows the Data Acquisition data flow for the four DSP channels. This block of IP Core modules delays and packetizes the AXI4−Stream data for output, and transmits the data to the PCIe interface using DMA. You can access register information by clicking on the blue blocks in the diagram.

The memory map for these FPGA IP Core modules is provided in Data Acquisition. For information about the corresponding support software, refer to Board Support Software: Navigator Design Suite.

Except for the Data Acquisition Interrupts Core, there are four copies of each IP Core described in the following topics: one for each Digital Signal Processing channel (Ch0, Ch1, Ch2, and Ch3).

• Pre−Trigger Control
• Data Flow Control
• DMA
• Data Acquisition Interrupts