Overview

The topics listed below describe operation of the Model 71861 hardware resources. The block diagram below shows the overall data flow of the 71861 (click on it to enlarge it).

These functional blocks are described in the topics listed below.

• Analog to Digital Input
• Timing and Synchronization
• Interrupt Operation
• FPGA System Monitor
• I2C Bus Controllers
• RAM Memory Operation
• FLASH Memory Operation

Refer to FPGA Core Operation for a description of the FPGA IP Core modules data processing.