A 128−MByte bank of FLASH memory is provided for processing FPGA boot code. Up to four FPGA boot configurations can be stored in FLASH, identified as Version 0, Version 1, Version 2, and Version 3. Version 0 is the Pentek−supplied default boot configuration (0 is the Gen 3 x8 PCIe code) and Versions 1, 2 and 3 are reserved for user−defined configurations.
At power−up, PCB switches SW1−3:4 designate which one of the FPGA configurations to boot from FLASH, as indicated in DIP Switch Settings.
FLASH memory is write−protected using PCB switch SW1−1. See DIP Switch Settings for these switch settings.
The table below shows the allocation of FLASH memory.
|
FLASH Boot Code |
Default Configuration Storage |
|---|---|
|
Version 0 Boot Code |
Gen 3 x8 PCIe (Pentek−supplied) |
|
Version 1 Boot Code |
Reserved |
|
Version 2 Boot Code |
Reserved |
|
Version 3 Boot Code |
Reserved |
|
The Versions 1, 2, and 3 Boot Code storage areas are blank as shipped from the factory. |
|
Use the Configuration Flash Access FPGA IP Core module to access FLASH memory.