AXI4-Stream Multiplexer IP Core - DDC Bypass Mux for Channels 0, 1, 2, and 3

Register Space Memory Map Channel 0 DDC Bypass Mux Base Address = BAR0 + 0x0200_B000 Channel 1 DDC Bypass Mux Base Address = BAR0 + 0x0210_B000 Channel 2 DDC Bypass Mux Base Address = BAR0 + 0x0220_B000 Channel 3 DDC Bypass Mux Base Address = BAR0 + 0x0230_B000
Register Name	Address Offset (Base Address+)	Access	Description
Selection Control Register	0x00	R/W	Controls the selection bits of the multiplexer.

Selection Control Register:

This is the Selection Control Register in the AXI4-Stream Multiplexer Core for Channels 0 through 3 of the DSP Block. This register selects between the bypassed AXI4-Stream data and the filtered AXI4-Stream data that is to be mapped to the output of the Multiplexer core.

Selection Control Register (Base Address + 0x00) Channel 0 DDC Bypass Mux Address = BAR0 + 0x0200_B000 Channel 1 DDC Bypass Mux Address = BAR0 + 0x0210_B000 Channel 2 DDC Bypass Mux Address = BAR0 + 0x0220_B000 Channel 3 DDC Bypass Mux Address = BAR0 + 0x0230_B000
Bits	Field Name	Default Value	Access Type	Description
31:3	Reserved	N/A	N/A	Reserved
2:0	select_bits	000	R/W	Select Bits: Determine which input is mapped to the output. 000 = Bypassed data from User Block 001 = Filtered DDC data other combinations = invalid

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Stream Multiplexer IP core, the IP user manual is in the file px_axis_pdti_mux.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Stream Multiplexer IP core, the corresponding BSP header file is px_axis_pdti_mux.h.