AXI4-Stream Mixer IP Core - DDC Mixer for Channels 0, 1, 2, and 3

This core serves as a 16-bit mixer for the input AXI4-Stream of the DSP Block.

Register Space Memory Map
Channel 0 DDC Mixer Base Address = BAR0 + 0x0200_1000
Channel 1 DDC Mixer Base Address = BAR0 + 0x0210_1000
Channel 2 DDC Mixer Base Address = BAR0 + 0x0220_1000
Channel 3 DDC Mixer Base Address = BAR0 + 0x0230_1000

Register Name

Address Offset

(Base Address+)

Access

Description

Mode Control Register

0x00

R/W

Controls mode of operation of the core.

Mode Control Register:

This register is used to control the mode of operation of the AXI4-Stream Mixer IP core used in the DSP Block for Channels 0 through 3.

Control Register (Base Address + 0x00)
Channel 0 DDC Mixer Address = BAR0 + 0x0200_1000
Channel 1 DDC Mixer Address = BAR0 + 0x0210_1000
Channel 2 DDC Mixer Address = BAR0 + 0x0220_1000
Channel 3 DDC Mixer Address = BAR0 + 0x0230_1000

Bits

Field Name

Default

Value

Access

Type

Description

31:2

Reserved

N/A

N/A

Reserved

1:0

mode

00

R/W

Mode of Operation: These bits define the mode of operation of the core.

00 = Bypass mode: Bypass input data to the output ports.

01 = Mixer mode: Performs multiplication of the input data streams to generate output data.

10 = Numerically Controlled Oscillator (NCO) mode: Bypasses input data from the NCO to the output ports.

11 = Zero mode: Output data tied to zeroes.

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Stream Mixer IP core, the IP user manual is in the file px_axis_mixer_1.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Stream Mixer IP core, the corresponding BSP header file is px_axis_mixer.h.