AXI4-Stream Multiplexer IP Core - Data Source Select Mux for Channels 0, 1, 2, and 3

Register Space Memory Map Channel 0 Data Source Select Mux Base Address = BAR0 + 0x0101_1000 Channel 1 Data Source Select Mux Base Address = BAR0 + 0x0102_1000 Channel 2 Data Source Select Mux Base Address = BAR0 + 0x0103_1000 Channel 3 Data Source Select Mux Base Address = BAR0 + 0x0104_1000
Register Name	Address Offset (Base Address+)	Access	Description
Selection Control Register	0x00	R/W	Controls the selection bits of the multiplexer.

Selection Control Register:

This is the Selection Control Register in the AXI4-Stream Multiplexer Core of the Data IO Interface Block. This register selects the ADC channel that is mapped to the output of the AXI4-Stream Multiplexer IP core.

Selection Control Register (Base Address + 0x00) Channel 0 Data Source Select Mux Address = BAR0 + 0x0101_1000 Channel 1 Data Source Select Mux Address = BAR0 + 0x0102_1000 Channel 2 Data Source Select Mux Address = BAR0 + 0x0103_1000 Channel 3 Data Source Select Mux Address = BAR0 + 0x0104_1000
Bits	Field Name	Default Value	Access Type	Description
31:3	Reserved	N/A	N/A	Reserved
2:0	select_bits	000	R/W	Select Bits: Determine which input is mapped to the output. 000 = ADC Channel 0 is output 001 = ADC Channel 1 is output 010 = ADC Channel 2 is output 011 = ADC Channel 3 is output 100 = Test Signal from Test Signal Generator is output Other combinations = invalid

For more information:

The Navigator FPGA Design Kit (FDK) provides a user manual for each IP core module. For the AXI4-Stream Multiplexer IP core, the IP user manual is in the file px_axis_pdti_mux.pdf.

The Navigator Board Support Package (BSP) provides a software interface to each IP core module. For the AXI4-Stream Multiplexer IP core, the corresponding BSP header file is px_axis_pdti_mux.h.