Model 71861 Memory Maps

Overview

The memory map tables describe access to the Model 71861 IP Core module resources from an external (off−board) PCIe Bus Master, such as an XMC baseboard processor. Memory maps to these resources are given from the baseboard processor’s viewpoint.

The Model 71861 is controlled from the XMC baseboard through a PCIe Bus interface. All 71861 resources are configured to be available in PCI Address Space, relative to PCI Base Address Register 0 as listed in the Model 71861 PCI Memory Map table. See PCI Configuration Space Registers for a summary of the PCI Configuration Space Registers.

Model 71861 PCI Memory Map
PCI Bus Address *	Modules
0x0000_0000	PCI Express Interfaces
0x0080_0000	Data Acquisition
0x0100_0000	Data I/O Interfaces
0x0200_0000	Digital Signal Processing
0x0300_0000	User Block Address Space
* All addresses are relative to PCI Base Address Register 0. Refer to the operating manual supplied with your XMC baseboard or carrier for the PCI Base Address settings.