Interrupts (top)

• #INT_vec  0x10  myfunction
• This will load  address of myfunction into 0x10 (SER1_VEC). myfuntcion will be called whenever the interrupt occurs.
• interrupt myfunction()
• Generates code to save restore registers when myfunction called.
  

• trap and nmi are non maskable interrupts. They have hardcoded jmp addresses
  
• All others are controlled by the interupt base register. Points to the 256 word page holding the interrupt vectors
• The  IEF1 bit is used to enable,disable interrupts
  
• DI sets IEF1 to 0  disabling interrupts
• EI sets IEF1 to 1 enabling interrupts.
• A second register sets the upper 3 bits of the interrupt vector address so interrupt vectors can be relocated within 32 byte blocks.
• Interrupt control Int/Trap control register: ITC:0X34
• B7: trap  - set to 1 when undefined opcode executed. non maskable
• B6:UFO - undefined fetch object.
• Tells which byte of a multibyte opcode fetch caused the trap.
• B2-0: ITE2-0 R/W interrupt enable external. ITE2,ITE1,ITE0 enable and disable interrupt inputs:INT2*,INT1*,INT0*. If reset to 0 then the interrupt is disabled.
  
• clock
• z180 i/o device register addresses
• 0x108: microprocessor clock speed in units of 1200 Hz (16 bits).
• 9.216 Mhz clock=7680,
• 18.432 Mhz clock = 15360.
• 0x16c long coef. relating speed of micro processor clock relative to speed of real time clock. Nominal value is 107324182 which is 1/40 of a second microprocessor time on the scale where 2^32-1 is 1 sec. 4 bytes of eeprom store least byte first.
  
• Timers:
• built into z180 (see user manul page 156)
• Are clocked at sysclock/20
• tmdr 16 bit data register
• rldr   16 bit reload regiser
• TCR - timer control register
• B7 - TIF1 timer interrupt flag timer1
• B6 - TIF0 timer interrupt flag timer0 (rtk)
• when tmdrN counts down  to 0. tifN is set
• if tieN bit is set then an interupt will be generated
  
• when when tcr is read and the higher or lower byte of tmdrN is read, then tifN is reset to 0.
• B5 = TIE1 timer1 interrupt enable
• B4 - TIE0 timer0 interrupt enable
• when tieN is  set to 1, tifN=1 will generate an interrupt
• when tieN is reset to 0, timer interrupt N is disabled.
• B1-0 -TDE1-0N Timer down count enable
• Enables (1) disables (0) downcounting for tmdr1,0.
  
• when set to 0 then tmdrN is freely read.
  
• Operation:
• tmdr decrements once every 20 sysclocks
• At 18.432Mhz  20/18.432e6= 1.05307 usecs per count
  
• When tmdr counts down to 0 , automatically reloaded with rldr
• You can read tmdr (moves to internal temp reg) while running
• To write to tmdr you must stop timer
• rldr  when witing, you need to make sure that a reload does not occur during the write (since it is 2 8 bit writes)..

How the timing  works:  (top)

Tiedown time systems:

• TMSCOUNTER:
• this is a 32 bit integer variable in the little star program. Its units are milliseconds.
  
• It gets incremented by 5 every time the control law routine is run.
• This  routine is scheduled to run every 5 milliseconds by the real time kernel of the little stars.
• The 1 second tick interrupt routine can make the following changes to tmscounter:
• The 1 sec tick routine resyncs the controlLaw to run 1 millisecond after every 1 sec tick
• This phases when the running of the controlLaw to the maser.
• It does not change the value of tmsCounter, just when it gets incremented.
  
• When tmsCounter is > then  86400000  it is set to 0 . this is the midnight  crossing.
• When vxWorks sends a setTime command, it will replace the current value of the tmsCounter with the value sent from vxWorks.
• This is how the time is synced to utc.
• pnt td time 0 performs this operation.
  
• Logging of tmsCounter:
• TmAtLast100ms:
• the control law routine computes: ( TmsCounter % 100 ) < 5). When this is  true, it places the current value of TmsCounter in ctrl.TimeAtLast100ms (as well as the position and load cell values).
  
• VxWorks queries each tiedown status after the 1 second tick. This reads the timeAtLast100ms as well as all the status variables. This can take many milliseconds.
• The normal read  order is td12,td4,td8. 
• The timeAtLast100ms read back is for second N is usually  td12: N.0, td4: N.0, td8: N.1
  
• td8 has .1 secs since by the time it is queried, 100 milliseconds has elapsed from the  1 second tick (this delay come from the serial i/o being only 38kb).
• By definition, tmsCounter always returns a value within 5 counts of a multiple of 100 milliseconds.
  
• TmAtLastSecTick:
• The 1 secd tick interrupt routine stores the value of tmsCounter whenever it runs. This value can be queried with the getTime command to see the time at the last 1 sec tick. This is done manually with the tieTst program. This value is not constrained to be within  5 counts of a multiple of 100 milliseconds
  
• little star RealTime clock  chip.
• the little star had a real time clock chip that keeps track of time. In the code it is referred to as CLOCK.
  
• The time can be set by the setClock command (currently only available via tieTst program).
• The time can be read with getclock command (currently only available via tieTst program).
• UTC:
• this is kept by the hydrogen maser. It is distributed via hardware 1 second ticks and irig signals.
• The vxWorks program syncs TMSCOUNTER  to UTC with the setTime command.
  
• This  occurs when:
• the vxWorks program starts
• The vxWorks program notices that a little star has rebooted.
• the user enters pnt td time 0...
• This is   sent whenever the operator enters tietrk.
• The 1 second tick routine resyncs the 5 millisecond  interval of the controllaw every 1 sec (but it does not change the current value of tmsCounter.
  

Running the controlLaw (PID) routine every 5 milliseconds:

 The controlLaw for the pid loop is scheduled every 5 milliseconds by the Real Time Kernel (RTK) running on the little star computers. A 16 bit timer register is used to generate the interrupt. It is driven by the 18.432Mhz oscillator on the little star. A one second tick (from the maser) interrupts once a second and rephases the 16 bit timer so the control law will run 1 millisecond after the 1 second tick. This happens every second (as long as the 1 second ticks are arriving).It the 1 second ticks do not arrive, then the rephasing does not occur and the 5 millisecond period can drift (since the little star oscillator isn't exactly 18.432 Mhz).
    The notes below show how this is done. The setup is done in the little star program tiedownq.c.

• The real time kernel uses timer0 (PRT0_VEC)  as the time base for the real time kernel.
• The timer interrupt runs a program to schedule the highest priority  program: (ControlLaw).
• #define TICK_FREQUENCY 4608
• This is passed to init_timer0(TICK_FREQUENCY)
  
• TICK_FREQUENCY loaded into timer control registers:  tmdr and rldr
  
• The timer decrements 1 for every 20 sysclocks. When tmdr counts down to 0 it generates an interrupt and then reloads rldr into tmdr.
  
• For sysclock=18.432Mhz  and a 5 millisecond update rate for control law:
  
• .005/ (20/18.432e6) = 4608.   so 4608 gives 5 millisecond rtk ControlLaw cycle.
• 1 second tick
• 1 sec tick receiver:
• Interrupt  arrives on fiber receiver (light level < -40dbm).
  
• Goes through 244 buffer driver   output as FO_IPP
• FO_IPP clocks a D flip flop.
• Q* output back to 244 buffer then out as /ls ipps_int (ls pin 12 input). This goes to INT2_VEC.
  
• Little star interrupt routine writes to digital out14. This resets the D-flipflop. Q* goes high and /ls_1pps_int goes back high (no interrupt).
  
• little star uses INT2_VEC .
  
• this is connected to digital input12
• the 1 sec tick rcvr board receives the tick via fiber and sendS the signal up to digital input 12 as a latched Q* output of a D flipflop
  
• Initializing 1 sec tick
  
• enabe1ppsint() sets itc 0x4 . this is the interrupt control reg. /int2 is b2.
• disable1ppint() set itc 0x4 to 0. 
• 1pps interrupt routine.
• disable 1pps interrupt. I thought interrupts were disabled on entry to interrupt routines. Maybe they are worrying about a plcbus interrupt (INT1_VEC) occurring while in the 1 sec tick interrupt routine?
  
• this just sets itc b2 to 0
• write 1 to digital out 14.  this resets the D flipflop on the 1pps rcvr board so the /ls_1pps_int goes high (not active)
• reload the tmdfr0 data register of timer0 to 800 usecs.. This rephases the rtk timer every  1 sec tick.
  
• tmdr0h = 0x02
• tmdr0l  = e0
• 0x02e0 = 736.
• 736*(20/18.432e6)= .799 millisecs. .. so .799 millisecs after the 1 sec tick routine, the rtk will reschedule the control law.
• Looking at the controLaw output bit at it's start.. it starts about 1.04 millisecs after 1pps at rcvr.
• 47 usecs to get to interrupt routine
• 800 usecs wait
• 150 usecs to reschedule controlLaw..
• I thought it was illegal to reload the tmdr register while it was down counting (according to the z180 manual page 158)
• Need to be careful that the tmdr is not close to 0 in the low byte when this occurs. If the lower byte rolls around when we write the new high byte, there could be problems.
  
• Once the timer0() phase is set to 800 usecs after the tick, every tick will then reset that phase to 800 usecs after the tick
• This is  why whenever we saw the left most timer0 interrupts drift, they would always get reset at the tick.
• Timing:
• 47 usecs 1 sec tick rcvr to start of 1pps interrupt routine (measured where the 2nd instrunction of 1pps routine: output(drv14,0xff)
• 27 usecs 1pps interrupt routine: drv14 high to drv14 low.
  
• Things to check:
• writing the tmdr0 register take 2 8byte writes. You need to make sure that the 16 bit number is not close to 0 on the lower 8 bits.
  
• If it rolled over during the update this could get out of sync.
• By measuring the time from start of controlLaw to 1 sec tick you should be able to compute how close you are..
• If you are close to a roll over, you could change the phase (800 usecs to something else).
  
• Changing the debug statements (output signals on ,off) could change this phase a little.
• Want to make sure that that no extra glitches of 1 sec tick away from the 1pps. 
• Unplug  the 1 sec tick inputs. Measure how fast the little star time drifts off. This will measure the actual freq of each little star oscillator.
  

<- page up
home_~phil