User Blocks

The FPGA provides two IP Core modules for user custom processing: User Block 1 and User Block 2. See Model 71861 FPGA Simplified Data Flow for the location of these User Blocks in the overall data flow.

In the default FPGA configuration, these User Blocks contain no data processing and are just pass−through functions. You can use the Navigator FPGA Design Kit (FDK) to create custom user IP code for these blocks. (The Navigator FDK provides the complete IP code for the 71861 Jade board. You can access every component of the Pentek design, replacing or modifying blocks, such as the User Blocks, as needed for your application. See Board Support Software: Navigator Design Suite for further description of the Navigator FDK.)

In addition, the FPGA reserves two blocks of PCI memory for user registers or data storage by the User Blocks. The memory map for the User Blocks’ register/storage space is provided in User Block Address Space.