Sync Bus

Model 71861 provides SYNC, GATE, and PPS signals for ADC and user applications. These signals can be driven from the front panel Sync Bus connector LVPECL or TTL inputs (see Front Panel Connections), the front panel TRIG SSMC connector input (see Trigger Input Connector), or a Gate/Sync/PPS Generate Register write.

When Model 71861 is a Sync/Gate Master, a Generate Register write, Sync Bus TTL input, or TRIG input signal is output to the Sync Bus LVPECL SYNC or GATE pins.

The diagram below illustrates the sync bus logic (click on it to enlarge it). Use the Sync Bus Interface FPGA IP Core module to control these signals.