71861_I2C_Bus

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I2C Bus 0

I2C Bus 0 is used to control several sensors and on−board clocks. Each I2C bus device has a separate bus address, listed in the I2C Port 0 Bus Addresses table below. Refer to the information identified in the table below for a description of the device's use in the 71861. Refer to a device’s datasheet (see Supporting Documentation) for a description of the device’s programmable registers. Use the I2C Port 0 FPGA IP Core module to access these devices.

I2C Port 0 Bus Addresses
Device	Address *	Information
Main PCB LM95234 Temperature Sensor	0011000h	Main PCB M95234 Temperature Sensor
Front Panel Module LM83 Temperature Sensor	0011001h	Front Panel Module LM83 Temperature Sensor
Main PCB LTC2990 Voltage Monitor	1001100h	Main PCB LTC2990 Voltage Monitor
Main PCB Si571 Programmable VCXO	1100000h	Si571 Programmable VCXO
Main PCB Silicon Labs Si5341B Clock Generator	1110100h	Si5341B AnyRate Clock Generator
* The bus addresses are 7−bit serial bus address, followed by the bus R/W bit h: 0 = Write, 1 = Read.

Main PCB M95234 Temperature Sensor

The LM95234 measures component temperatures on the 71861 main PCB, and provides an alarm when any exceeds its programmable limit. The table below lists the LM95234 sensor inputs:

Main PCB LM95234 Programmable Sensors
Monitored Condition	LM95234 Input	Navigator Limits *
FPGA temperature	1	100° C
Power Supplies	2	60° C
Power Supplies	3	60° C
CDCM7005	4	60° C
LM95234 Local	(internal)	50° C
* These limits are programmed if you run the Pentek Navigator 71861 Hardware Monitor routines for the LM95234 using the default values.

When any of the inputs exceeds the high setpoint limit, a red LED on the main 71861 PCB is illuminated (see PCB LEDs).

Front Panel Module LM83 Temperature Sensor

The LM83 measures component temperatures on the 71861 front panel module PCB, and provides an alarm when any exceeds its programmable limit. The table below lists the LM83 programmable sensor inputs:

Front Panel LM83 Programmable Sensors
Monitored Condition	LM83 Input	Navigator Limits *
Near ADC0	1	85° C
Near ADC3	2	85° C
Near ADC1 & 2	3	85° C
LM83 Local	(internal)	85° C
* These limits are programmed if you run the Pentek Navigator 71861 Hardware Monitor routines for the LM83 using the default values.

When any of the inputs exceeds the high setpoint limit, a red LED on the main 71861 PCB is illuminated (see PCB LEDs).

Main PCB LTC2990 Voltage Monitor

The Linear Technology LTC2990 voltage, current, and temperature monitor measures main PCB voltage. Two voltage inputs are required for monitoring power, so the Navigator software is configured for two inputs for 12V and two inputs for 3.3V. The table below lists the inputs on the LTC2990:

Main PCB LTC2990 Inputs
Monitored Condition	LTC2990 Input	Navigator Limits *
12V / 5V voltage	V1	High Limit = 12.60 V / 5.25 V Low Limit = 11.40 V / 4.75 V
12V / 5V voltage	V3	High Limit = 12.60 V / 5.25 V Low Limit = 11.40 V / 4.75 V
3.3V voltage	V2	High Limit = 3.465 V Low Limit = 3.135 V
3.3V voltage	V4	High Limit = 3.465 V Low Limit = 3.135 V
* These limits are programmed if you run the Pentek Navigator 71861 Hardware Monitor routines for the LTC2990 using the default values.

Si571 Programmable VCXO

The Silicon Labs Si571 programmable Any−Rate VCXO generates the on−board clock for the CDCM7005 Clock Synthesizer. The Si571 output frequency is determined by programming the oscillator frequency and the output dividers using onboard registers. The default VCXO frequency output is set for 200 MHz.

Take care that the ADC clock output from the CDCM7005 never exceeds the ADS5485’s rated clock speed during any change of frequency with the VCXO and/or the CDCM7005.

− If you are increasing the VCXO frequency, first adjust the appropriate CDC divider so that the ADS5485 clock does not exceed 200 MHz.

− If you are decreasing the VCXO frequency, do not adjust the CDC divider until the VCXO has been reprogrammed so that the ADS5485 clock does not exceed 200 MHz.

Si5341B AnyRate Clock Generator

The Si5341B creates the FPGA Configuration clock, FPGA 200MHz Reference Clock, FPGA P16 Gigabit IO clock, DDR4 controller reference clock, and an optional 100MHz PCIe clock when no host clock is available. The following Si5341B outputs are used in the Model 71861 (OUT1, OUT3, and OUT6 are not used):

Clock	71861 Use	Default
OUT0	PCIe Clock	100 MHz
OUT2	DDR4 Controller Reference Clock	240.096 MHz
OUT4	FPGA Reference Clock	200 MHz
OUT5	FPGA P16 Gigabit IO clock	156.25 MHz
OUT7,8	FPGA Configuration Clock	100 MHz
OUT9	Auxiliary FPGA Clock − available for custom FPGA design	100 MHz

Only the FPGA P16 Gigabit IO clock (OUT5) or Auxiliary FPGA Clock (OUT9) should ever be changed. FPGA P16 Gigabit IO clock defaults to 156.25 MHz, used by 10GE or some Aurora frequencies.