Clocks

Model 71861 clocks can be selected from the front panel Sync Bus LVPECL CLK input (see Front Panel Connections), the front panel SSMC CLK input (see Clock Input Connector), or the onboard Si571 VCXO. The selected clock source is input to a CDCM7005 Clock Synthesizer that generates five output clocks, each independently programmable. CDCM7005 clock Y0 provides the sample clock for the four ADS5485 ADCs, and clock Y2 provides FPGA CLK for ADC data processing in the FPGA.

When the Model 71861 is a Clock Master, CDCM7005 clock Y4 is output to the CLK pins of the Sync Bus (see Front Panel Connections).

The drawing below illustrates the clock logic (click on it to enlarge it). Use the CDCM7005 Control & Clock Generation FPGA IP Core modules to control these clock signals.