XMC Connectors

Model 71861 provides an XMC high−speed serial connector, identified as P15, that complies with the VITA 42.3 XMC Switched Mezzanine Card Auxiliary Standard. This interface is configured as PCI Express Gen 3 x8.

Option 105 for the 71861 provides high−speed serial connections from FPGA spare pins using XMC connector P16. This connector complies with the VITA 42.0 XMC Standard and can support various interfaces including VITA 42.2 Serial RapidIO, VITA 42.3 PCI Express, or VITA 42.5 Aurora.

The table below identifies the FPGA to XMC P16 pin connections.

Option 105 XMC P16 FPGA Pin Connections

Pin

A

B

C

D

E

F

01

S2_TD_P0

S2_TD_N0

n/c

S2_TD_P1

S2_TD_N1

n/c

02

GND

GND

n/c

GND

GND

n/c

03

S2_TD_P2

S2_TD_N2

n/c

S2_TD_P3

S2_TD_N3

n/c

04

GND

GND

n/c

GND

GND

n/c

05

S3_TD_P0

S3_TD_N0

n/c

S3_TD_P1

S3_TD_N1

n/c

06

GND

GND

n/c

GND

GND

n/c

07

S3_TD_P2

S3_TD_N2

n/c

S3_TD_P3

S3_TD_N3

n/c

08

GND

GND

n/c

GND

GND

n/c

09

n/c

n/c

n/c

n/c

n/c

n/c

10

GND

GND

n/c

GND

GND

n/c

11

S2_RD_P0

S2_RD_N0

n/c

S2_RD_P1

S2_RD_N1

n/c

12

GND

GND

n/c

GND

GND

n/c

13

S2_RD_P2

S2_RD_N2

n/c

S2_RD_P3

S2_RD_N3

n/c

14

GND

GND

n/c

GND

GND

n/c

15

S3_RD_P0

S3_RD_N0

n/c

S3_RD_P1

S3_RD_N1

n/c

16

GND

GND

n/c

GND

GND

n/c

17

S3_RD_P2

S3_RD_N2

n/c

S3_RD_P3

S3_RD_N3

n/c

18

GND

GND

n/c

GND

GND

n/c

19

XMC_REFCLK1_P

XMC_REFCLK1_N

n/c

n/c

n/c

n/c

Sn_TD_Pm, Sn_TD_Nm = Serial Transmit, FPGA Auxiliary Port n, lane m
Sn_RD_Pm, Sn_RD_Nm = Serial Receive, FPGA Auxiliary Port n, lane m