The Timestamp Generator Interface IP Core accepts input Timing Event AXI4−Streams (Gate, Sync, and PPS) from the Sync Bus. These signals are used to control the generation of a timestamp output AXI4−Stream which provides counts of sample clock cycles and PPS events for use by all four ADC channels.
Click on Timestamp Generator Interface IP Core - Timestamp Generator to access register information.
Refer to the Pentek Navigator Timestamp Generator IP Core Manual for a description of this IP module.