Channel Nomenclature

The Model 71861 has four analog inputs to the ADS5485 ADCs, identified on the front panel as IN 1, IN 2, IN 3, and IN 4. All references to the hardwired digital outputs from the ADS5485 ADCs and their signal connections to the FPGA use the numbers 1 through 4 to identify the associated input connector.

The 71861 FPGA IP code has four input interface cores (ADC Interface Cores): one for each front panel input, that are identified as ADC0 through ADC3. These are allocated to the four input signals as follows:

Front Panel Input	ADC Code Channel
IN 1	ADC0
IN 2	ADC1
IN 3	ADC2
IN 4	ADC3

In addition, the 71861 FPGA IP code has four Digital Signal Processing channels that are identified as Ch0, Ch1, Ch2, and Ch3. These are not allocated to specific ADC Interface Core channels and must be allocated by the user (see Channel Data Source Select Cores).

In the functional descriptions of the 71861 FPGA IP code, whenever the signal inputs are referenced, the nomenclature is in accordance with the front panel signal input connector numbers (1 through 4), and whenever the FPGA IP code processing is referenced, the nomenclature is in accordance with the ADC interface code channel numbers (0 through 3) or the DSP channel numbers (0 through 3).

When referencing any signal inputs in the Pentek Model 71861 front panel I/O module schematic drawings or in the Pentek Model 71861 Navigator FPGA Design Kit, the nomenclature is in accordance with the ADC code channel numbers, 0 through 3.