Analog Signal Inputs
Connectors: Four front panel SSMC connectors: IN 1, IN 2, IN 3, & IN 4
Input Type: Single−ended, non−inverting
Full Scale Input: +8 dBm
Maximum Power Input: 14 dBm
Coupling: Transformer coupled
Input Impedance: 50 ohms
Analog Input Transformers:
3dB Passband: 300 kHz to 700 MHz
Insertion Loss: 0.58 dB max.
Analog to Digital Converters
Quantity: Four Texas Instruments ADS5485 A/D converters
Sampling Rate: 10−200 MHz
Resolution: 16 bits
Clock Source: Selectable from onboard VCXO, front panel SSMC clock, or Sync Bus LVPECL clock input
Digital Downconverters (four separate channels)
Decimation Range: 2 to 32,768 in three stages of 2 to 32
LO Tuning Freq. Resolution: 32 bits, 0 to ƒs
LO SFDR: >120 dB
Phase Offset Resolution: 32 bits, 0 to 360 degrees
FIR Filter: 24−bit coefficients (user−programmable)
24−bit output
Default Filter Set: 80% bandwidth
<0.3 dB passband ripple
>100 dB stopband attenuation
Sync Bus Inputs/Outputs
Connector Type: Front panel 26−pin connector, SYNC/GATE
Signals:
CLK In/Out: 2 pins (LVPECL pair)
GATE In/Out: 2 pins (LVPECL pair)
SYNC In/Out: 2 pins (LVPECL pair)
LVTTL GATE/TRIG In: 1 pin (single−ended)
LVTTL SYNC/PPS In: 1 pin (single−ended)
Spares: 6 pins (3 LVPECL pairs)
Grounds: 12 pins
Bus Master/Slave: Bus master or bus slave mode selectable via software
Bus Termination: Bus termination provided by in−line cable end terminator
Number of Boards Supported: Up to four boards can be synchronized with a ribbon cable. Systems requiring more synchronized channels can be supported with the Model 7893 Clock Synthesizer.
Clock
Clock Source: Selectable from external or internal clock
External: Front panel SSMC CLK, or Sync Bus LVPECL CLK
Internal: Generated from programmable VCXO
External Clock Input
Connector Type: Front panel SSMC connector, CLK
Signal Type: Sine wave
Frequency Range: 10 to 800 MHz divider input clock or PLL system reference
(when greater than 200 MHz, the input clock must be divided down by the CDCM7005 for the ADC clock)
Voltage Range: +0 to +10 dBm
Coupling: AC coupled
Input Impedance: 50 ohms
Internal Sample Clock
Device: Silicon Labs Si571 Any−Rate VCXO
Type: Programmable VCXO
Frequency Range: 10−810 MHz
Start−Up Freq: 200 MHz
Freq Resolution: 0.09 ppb
Interface: FPGA I2C Bus 0
Clock Synthesizer
Device: Texas Instruments CDCM7005 Clock Synthesizer
Frequency Dividers: 1, 2, 4, 6, 8, and 16
Output Clocks:Five LVPECL output clocks
Interface: FPGA
Gate
Gate Sources: Selectable from external or internal gate
External: Front panel SSMC TRIG, or Sync Bus LVPECL GATE
Internal: Generated from programmable register
Gate Polarity: Programmable polarity for external gate
Triggering: Gate can be programmed as a trigger with a programmable trigger length
Sync
Sync Source: Selectable from external or internal sync
External: Front panel SSMC TRIG, or Sync Bus LVPECL SYNC
Internal: Generated from programmable register
Sync Pulse Width: 2 clock cycles, minimum
External Trigger Input
Connector Type: Front panel SSMC connector, TRIG
Signal Type: LVTTL
Field−Programmable Gate Arrays (FPGA)
Standard: Xilinx Kintex UltraScale XCKU035−2
Option 084: Xilinx Kintex UltraScale XCKU060−2
Option 087: Xilinx Kintex UltraScale XCKU115−2
Configuration: Factory programmed by Pentek: A/D, DDC, IP Cores
FPGA MGT Clock Generator
Device: Silicon Labs Si5341B Any−Rate Clock Generator
Type: 10 separate programmable clock outputs
Frequency Range: 100 Hz to 350 MHz
Interface: FPGA I2C Bus 0
RAM memory
Size: 5 Gigabytes of DDR4 SDRAM
Speed: 1200 MHz (2400 MHz DDR)
Bus Width: 80 bits
Interface: FPGA
Configuration FLASH memory
Size: 1 Gigabit
Bus Width: 16 bits
Interface: FPGA
XMC Interfaces
PCI Express Interface
XMC Connector: 114−pin (XMC standard Pn5 connector), P15
Compliance: ANSI/VITA 42.3 XMC PCI Express Protocol Standard
Lanes/Speed:
Gen1 x8 − 2 GB/sec
Gen2 x8 − 4 GB/sec
Gen3 x8 − 8 GB/sec
Secondary XMC Interface (Option 105)
XMC Connector: 114−pin (XMC standard Pn6 connector), P16
Compliance: ANSI/VITA 42.0 XMC Standard
Protocol (user must implement these protocols with user FPGA code):
ANSI/VITA 42.2 XMC Serial RapidIO Protocol Standard
ANSI/VITA 42.3 XMC PCI Express Protocol Standard
ANSI/VITA 42.5 Aurora Pin Assignments
PMC Interface (Option 104)
PMC Connector: 64−pin PMC standard Pn4 connector, P14
Compliance: 48 I/O lines routed to the FPGA as 24 LVDS pairs or 48 LVCMOS single−ended (2.5V)
Note: Not 3.3V tolerant
Temperature and Voltage Sensors
Main PCB Temperature
Quantity: Four temperature sensors
Controller: Texas Instruments LM95234
Interface: FPGA I2C Bus 0
Main PCB Power
Quantity: Four voltage inputs (two for 3.3V, two for 12V)
Controller: Linear Technology LTC2990
Interface: FPGA I2C Bus 0
Main PCB Voltage
Quantity: Ten voltage sensors
Controller: Kintex UltraScale System Monitor
Interface: FPGA
Front Panel Interface Module Temperature
Quantity: Three temperature sensors
Controller: Texas Instruments LM83
Interface: FPGA I2C Bus 0
| Current Draw: | +3.3V (Watts) | VPWR (12V or 5V) (Watts) | Total |
|---|---|---|---|
| XCKU035 (Standard) | TBD | TBD | TBD |
| XCKU060 (Option 084) | 4.79 | 32.61 | 37.4 |
| XCKU115 (Option 087) | 2.68 | 37.33 | 40.02 |
|
*With factory IP at the maximum clock rate. |
|||
Physical
Dimensions: Single PMC/XMC board
Depth: 149.0 mm (5.87 in)
Height: 74 mm (2.91 in)
Weight: Approximately 14 oz (400 grams), with 2−slot heatsink
Environmental
Standard: Level L0
Cooling Method (operational): Forced Air
Operating Temp: 0° to 50° C
Storage Temp: –20° to 90° C
Relative Humidity: 0 to 95%, non−condensing
Pentek Ruggedization Level L1
Pentek Option Number: −701
Cooling Method (operational): Forced Air
Operating Temperature: 0° to 50° C
Storage Temperature: −40° C to +100° C
Sine Vibration: 2g, 20−500 Hz
Random Vibration: 0.01g2/Hz, 20−2000 Hz
Shock: 10g, 11ms
Relative Humidity:
No conformal coating: 0% to 95% non−condensing
Conformal coating (Option 720): 0% to 100% non−condensing
Pentek Ruggedization Level L2
Option Number: −702
Cooling Method (operational): Forced Air
Operating Temperature: −20° to 65° C
Storage Temperature: −40° C to +100° C
Sine Vibration: 2g, 20−500 Hz
Random Vibration: 0.04g2/Hz, 20−2000 Hz
Shock: 20g, 11ms
Relative Humidity:
No conformal coating: 0% to 95% non−condensing
Conformal coating (Option 720): 0% to 100% non−condensing
Pentek Ruggedization Level L3
Option Number: −713
Cooling Method (operational): Conduction Cooled
Operating Temp: –40° to 70° C
Storage Temp: –50° to 100° C
Relative Humidity: 0 to 95%, non−condensing