Digital Downconversion

The 71861 provides four DDC IP Core channels. Because of the flexible input routing of A/D Acquisition, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC.

Each DDC has an independent 32−bit tuning frequency setting that ranges from DC to ƒs, where ƒs is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 32,768 providing a wide range to satisfy most applications.

The decimating filter for each DDC accepts a unique set of user−supplied 24−bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒs/N, where N is the decimation setting. The rejection of adjacent−band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24−bit I + 24−bit Q or16−bit I + 16−bit Q samples at a rate of ƒs/N.