#TITLE    'DDSPAL10.SRC';
#ENGINEER 'Bill Sisk';
#COMPANY  'Arecibo Observatory';
#REVISION '0';
#PROJECT  'DDS Controller IPack Board (for printed circuit board)';
#COMMENT  'Using 22V10';  

"The interrupts are falling edge triggered on the Motorola 162 board.
"IntReq1 is used for the 1 sec tick interrupt. 
"Note that the interrupts are not registered. 
"The reason is that if the interrupt is registered, on power-up of the 
"the Motorala 162 board, the register may not be cleared. The sequence
"is that 30sec after power-up, an /IPReset occurs for 200ms. This would clear the
"register. The interrupt is then enabled on the 162 board.  However, if the
"tick occurs after the /IPReset and before the enabling of the interrupt, an 
"/IntSel cycle will never occur and the /IntReq1 register would never be cleared.
"Because the interrupts are edge triggered, we can disregard from the IP spec. that 
"says that the interrupt request lines must stay active until the /IntSel cycle occurs.

INPUT CLK,/IOSEL,/INTSEL,/IDSEL,RW,/RES,A1,/INT0,/INT1;
OUTPUT WRT, /RD, /ACK, OE CLOCKED_BY CLK RESET_BY RES;
OUTPUT D0 ENABLED_BY OE;
OUTPUT /INTREQ1, /INTREQ0, NC[3] ;


ACK = IOSEL + INTSEL + IDSEL;
WRT = IOSEL * /RW ;
RD = IOSEL * RW;
OE = INTSEL * A1;
D0 = 0;
INTREQ1 = INT1 * /RES;
INTREQ0 = INT0 * /RES;
NC = [0,0,0];                               
